1. Field of the Invention
The present invention relates generally to semiconductor device fabrication techniques using ULSI (ultra-large-scale integration) technology, and more specifically to a method of effectively lowering boron (B) concentration at an interface between an epitaxially grown film and the Si substrate surface. Such a film may be a Si or Si.sub.1-x Ge.sub.x film selectively deposited in an UHV-CVD (ultrahigh vacuum/chemical vapor deposition) apparatus using a source gas(es) such as SiH.sub.4, Si.sub.2 H.sub.6, GeH.sub.4, etc.
2. Description of the Related Art
It is known in the art that the selective epitaxial growth of Si or Si.sub.1-x Ge.sub.x on a silicon wafer surface, using an UHV-CVD apparatus with a source gas(es) such as SiH.sub.4, Si.sub.2 H.sub.6, or GeH.sub.4, has found an extensive application in forming about 0.1 .mu.m level of channel epitaxial construction in a miniaturized MOS (metal-oxide semiconductor) transistors, next generation's high-speed bipolar transistors, etc.
Before turning to the present invention, it is deemed advantageous to describe, with reference to FIGS. 1(A)-1(C), 2, and 3, conventional techniques relating to the present invention. Throughout the instant disclosure, term "substrate" is interchangeably used with "wafer". Although a high-speed bipolar transistor is referred to in this specification, it should be noted that the present invention is in no way limited thereto.
FIGS. 1(A)-1(C) are schematic cross-sectional views depicting the fabrication of a high-speed NPN bipolar transistor. In brief, a substrate wherein a collector portion has been formed as shown in FIG. 1(A), is transferred to an UHV-CVD apparatus such as that is schematically shown in FIG. 2. In the UHV-CVD apparatus, a Si or Si.sub.1-x Ge.sub.x epitaxial base portion is grown on the substrate as illustrated in FIG. 1(B). Following this, the wafer (or substrate) is removed from the UHV-CVD apparatus and an emitter portion is formed on the substrate in the manner shown in FIG. 1(C).
The present invention is directed to effective reduction of boron contamination (or concentration) at an interface between an epitaxially grown film and the Si substrate surface. To this end, each wafer is pretreated before being loaded into the CVD apparatus, and/or a growth chamber of the CVD apparatus is cleaned prior to each CVD process. Thus, it will be understood that the formation of the emitter portion shown in FIG. 1(C) is not relevant to the present invention.
Referring to FIG. 1(A), an N.sup.+ layer 10 is grown on an P.sup.+ &lt;100&gt;-oriented Si substrate 12 with resistivity ranging from 10 to 20 .OMEGA.cm (for example). Following this, an N.sup.- epi-layer 14, which functions as a collector, is deposited on the N.sup.+ layer 10. Further, as illustrated in FIG. 1(A), a SiO.sub.2 layer 16, a P.sup.+ poly-Si layer 18, and another SiO.sub.2 layer 20 are successively formed using conventional lithography and etching techniques.
The substrate, which has undergone the above processes, is transferred to the UHV-CVD apparatus wherein the Si or Si.sub.1-x Ge.sub.x epitaxial base (denoted by numeral 22) is selectively grown on the N.sup.- epi-layer 14. In this case, inner portions of the poly-Si layer 18 grow downwardly as schematically shown in FIG. 1(B). Subsequently, the substrate shown in FIG. 1(B) is unloaded from the UHV-CVD apparatus, after which a SiO.sub.2 layer 24 and an N.sup.+ poly-Si emitter layer 26 are formed, as shown in FIG. 1(C), using conventional techniques. The processes for forming the structure shown in FIGS. 1(A)-1(C) are well known and not directly concerned with the present invention, and thus further description thereof will be omitted for brevity.
FIG. 2 is a diagram schematically showing one example of an UHV-CVD apparatus (denoted by numeral 30), which comprises a robotic transfer section 32, two load-lock chambers 34a and 34b, another robotic transfer section 36, and two growth chambers 38a and 38b. The UHV-CVD apparatus 30 per se is well known in the art. Other sections such as turbo pumps, which are irrelevant to the present invention, are not shown in FIG. 2 for the sake of simplifying the disclosure. FIG. 2 will also be referred to in the preferred embodiments of the present invention.
The robotic transfer section 32 comprises a clean bench 40 and two substrate transfer robots 42a and 42b, while the robotic transfer section 36 includes a similar substrate transfer robot 44.
Each of the substrates or wafers, which has been processed as shown in FIG. 1(A), is cleaned and then disposed in a substrate carry box 46a which is, in this case, positioned in a place other than on the clean bench 40. This box 46a is then transported to the clean bench 40, as illustrated in FIG. 2. The precleaned wafers contained in the box 46s are loaded on a one-by-one basis, using the robot 42a, into the load-lock chamber 34a. After all the wafers in the box 46a are loaded into the load-lock chamber 34a, the chamber 34a is pumped down to a predetermined pressure. Once the predetermined pressure is reached, the first wafer in the load-lock chamber 34a is introduced, by way of the robot 44, into the growth chamber 38a which is dedicated to non-doping epitaxial growth.
After the epitaxial growth is completed in the chamber 38a, the wafer is conveyed to another growth chamber 38b which is dedicated to p-type (viz., B) doping epitaxial growth. The reason why the two growth chambers 38a and 38b are used will be described later. When the film deposition on the wafer at the chamber 38b is finished, the wafer is transferred to the load-lock chamber 34b. These processes are repeated with each of the wafers stored in the load-lock chamber 34a. When all the wafers in the load-lock chamber 34a are processed and loaded into the other load-lock chamber 34b, they are placed into another substrate carry box 46b by the robot 42b. The wafers in the box 46b are then transported to the next wafer process station, wherein subsequent wafer treatments, such as referred to with respect to FIG. 1(C), are implemented.
FIG. 3 is a flow chart depicting the steps that characterize the conventional processes which include cleaning and CVD processes. In more specific terms, the Si wafers, on which layers or films shown in FIG. 1(A) are formed, are precleaned and then transferred to the UHV-CVD apparatus 30 shown in FIG. 2.
Referring to FIG. 3, at step 50, each Si wafer undergoes a dilute HF (hydrofluoric acid) dip in order to remove native oxide formed on the wafer, after which the chemicals used in step 50 are removed by water washing (step 52). Immediately thereafter, at step 54, the wafer is subjected to a well known RCA cleaning process using a cleaning solution, NH.sub.4 OH (ammonia)-H.sub.2 O.sub.2 (hydrogen peroxide)-H.sub.2 O (pure water), thereby removing particles and organic contaminations on the wafer. The cleaning with the aforesaid solution is called "standard cleaning 1 (SC-1)), at NH.sub.4 OH--H.sub.2 O.sub.2 --H.sub.2 O (=1:1.5) (for example) at 60 to 80.degree. C. for 3 to 10 minutes. Following this, at step 56, the reagents used in step 54 are washed away using pure water, and the wafer is then dried using a spin dryer (step 58). The above mentioned wafer cleaning is carried out with each of a predetermined number of the wafers. Subsequently, the precleaned Si wafers are accommodated in the box 46a (FIG. 2) and transported to the clean bench 40 of the UHV-CVD apparatus 30 (FIG. 2).
The Si wafers in the wafer carry box 46a are then successively loaded into the load-lock chamber 34a (step 60). At step 62, a first wafer in the load-lock chamber 34a is loaded into the growth chamber 38a by way of the wafer transfer robot 44. When the first wafer is placed in the growth chamber 38a, the chamber is pumped down to a pressure of 10.sup.-9 to 10.sup.-10 torr. At step 64, the wafer is subjected to a high-temperature treatment (viz., high-temperature flashing) in the growth chamber 38a at more than 900.degree. C. for about 5 minutes in order to remove the native oxide on the wafer. At step 66, a temperature of the wafer is lowered to 600-800.degree. C., after which selective Si or Si.sub.1-x Ge.sub.x non-doped epitaxial growth is carried out on the wafer using a source gas(es) selected among SiH.sub.4, Si.sub.2 H.sub.6, GeH.sub.4, etc. as is well known in the art.
Subsequently, the flow proceeds to step 68 whereat the wafer is transferred to the growth chamber 38b. At step 70, a boron-doped selective Si or Si.sub.1-x Ge.sub.x epitaxial growth is implemented on the wafer, wherein diborane (B.sub.2 H.sub.6) is used as a dopant gas for forming a p-type base layer. In the above, the wafer is transferred from the chamber 38a to the chamber 38b in a vacuum environment thus obviating the need for implementing the high-temperature flashing on the wafer in the growth chamber 38b. At step 72, the wafer on which the p-type base layer has been grown is loaded into the load-lock chamber 34b. Thereafter, the next wafer in the load-lock chamber 34a is introduced into the growth chamber 38a from the load-lock chamber 34a and is subjected to the above mentioned processes. At step 74, a check is made to determine if all the wafers in the load-lock chamber 34a are processed. If the answer to the inquiry made at step 74 is affirmative (viz., YES), the flow shown in FIG. 3 is terminated.
The above mentioned known wafer processing steps, however, suffer from the problem that the selective Si or Si.sub.1-x Ge.sub.x epitaxial growth on the wafer undesirably leaves "boron contamination" at the boundary between the epitaxial layer and the substrate surface. The boron concentration typically exhibits more than 1E17 (i.e., 1.times.10.sup.17) atoms/cm.sup.3 at peak concentration and 1E12 atoms/cm.sup.2 at sheet concentration. The causes of such a high boron concentration are as follows.
(1) Boron is contained in the cleaning solution used in the RCA cleaning process. For example, in the case where the solution is a composition of Ammonia-"Hydrogen Peroxide"-"pure water"=1:1.5, boron in the order of about 100 ppt (parts per trillion) is present in the above-mentioned standard cleaning (SC-1) solution. Thus, when a wafer is subjected to the conventional RCA cleaning, boron is undesirably absorbed into or included in the native oxide.
(2) In the clean room, the filtered air flows from ceiling to floor. Such a filter ceiling system includes a borosilicate glass fiber filter such as ULPA (ultra low penetration air) filter, HEPA (high efficiency particulate air) filter, etc. The descending airflow contains boron resulting from the glass fiber filters. Further, these filters are unable to successfully strain out boron which is contained in the outside (viz., open) air which is introduced to the clean room. As a result, boron is inherently present in the clean room environment. Thus, the boron concentration in the SC-1 solution is further enhanced with the result of additional boron being taken into the native oxide. Still further, during the steps 50, 52, 56, 58 and 60 (FIG. 3), boron tends to adhere, in the clean room environment, to the native oxide developed on the wafer.
(3) Boron which is adhered to the native oxide remains on the wafer even if the native oxide is removed by the high-temperature flashing in the growth chamber.
The above mentioned high boron concentration at the interface between the epitaxial layer and the surface of the Si wafer, undesirably lowers a cut-off frequency of a high-speed bipolar transistor, and causes variation of the threshold voltage in the case of miniaturized CMOS transistors.
One approach to reducing the boron contamination is disclosed in Japanese Laid-open Patent Application No. 4-97517. According to this prior art, a wafer which has been subjected to the RCA cleaning is treated using dilute HF and then cleaned using water whereby boron is removed as BF.sub.3. The prior art, however, has encountered the difficulty that the surface of the wafer is exposed to an ambient clean room atmosphere and thus, the wafer is susceptible to organic and/or inorganic contamination which cannot be removed even by the high-temperature flashing in the growth chamber.